Use the new inputs to determine the next state: Q2 and Q1 will latch and Q0 will toggle.ģ. Put the counter in an arbitrary state then determine the inputs for this state.Ģ. Start by setting up the outputs as shown, then write the logic equation for each input. Summary Analysis of Synchronous Counters A tabular technique for analysis is illustrated for the counter on the previous slide. Notice the inputs to each flip-flop… Floyd, Digital Fundamentals, 10th ed
Digital fundamentals 10th edition chapter 8 how to#
The next slide shows how to analyze this counter by writing the logic equations for each input.
This 3-bit binary synchronous counter has the same count sequence as the 3-bit asynchronous counter shown previously.
Synchronous counters overcome the disadvantage of accumulated propagation delays, but generally they require more circuitry to control states changes. Summary Synchronous Counters In a synchronous counter all flip-flops are clocked together with a common clock pulse. CLK BĪll J and K inputs are connected internally HIGH Two inputs are provided that clear the count. The counter can be extended to form a 4-bit counter by connecting Q0 to the CLK B input. Summary The 74LS93A Asynchronous Counter The 74LS93A has one independent toggle J-K flip-flop driven by CLK A and three toggle J-K flip-flops that form an asynchronous counter driven by CLK B. The sequence is 0 – 2 – 1 – (CLR) (repeat)… Floyd, Digital Fundamentals, 10th ed Summary CLK LSB MSB CLR Note that it is momentarily in state 3 which causes it to clear. The next slide shows the scope… Floyd, Digital Fundamentals, 10th ed The counter in this slide is a Multisim simulation of one described in the lab manual. Summary Asynchronous Counter Using D Flip-flops D flip-flops can be set to toggle and used as asynchronous counters by connecting Q back to D. Summary Asynchronous Decade Counter When Q1 and Q3 are HIGH together, the counter is cleared by a “glitch” on the CLR line. Other truncated sequences can be obtained using a similar technique.
The flip-flops are trailing-edge triggered, so clocks are derived from the Q outputs. Summary Asynchronous Decade Counter This counter uses partial decoding to recycle the count sequence to zero after the 1001 state. Q0 is delayed by 1 propagation delay, Q2 by 2 delays and Q3 by 3 delays. Notice how delays are cumulative as each stage in a counter is clocked later than the previous stage. For certain applications requiring high clock rates, this is a major disadvantage. Summary Propagation Delay Asynchronous counters are sometimes called ripple counters, because the stages do not all change together. The resulting sequence is that of an 3-bit binary up counter. The leading edge of Q0 is equivalent to the trailing edge of Q0. The following stage is triggered from Q0. Summary Three bit Asynchronous Counter Notice that the Q0 output is triggered on the leading edge of the clock signal. Waveforms are on the following slide… Floyd, Digital Fundamentals, 10th ed
It uses J-K flip-flops in the toggle mode. The three-bit asynchronous counter shown is typical. Subsequent stages derive the clock from the previous stage. Summary Three bit Asynchronous Counter In an asynchronous counter, the clock is applied only to the first stage. The first stage in the counter represents the least significant bit – notice that these waveforms follow the same pattern as counting in binary. Summary Counting in Binary A counter can form the same pattern of 0’s and 1’s with logic levels. © 2009 Pearson Education, Upper Saddle River, NJ 07458. The next bit changes on every other number. 000 001 010 011 100 The next bit changes on 101 every fourth number. Summary Counting in Binary As you know, the binary count sequence follows a familiar pattern of 0’s and 1’s as described in Section 2-2 of the text. 2008 Pearson Education © 2009 Pearson Education,© Upper Saddle River, NJ 07458.